This invention relates to semiconductor memories comprising a plurality of memory cells each including a non-volatile memory transistor. The semiconductor memory may be part of a monolithic semiconductor device formed in, for example, monocrystalline silicon. However the invention is particularly advantageous for forming the memory in thin-film circuitry on an insulating substrate as part of a larger area electronic device which also includes other thin-film circuitry on the insulating substrate. The other thin-film circuitry may perform a logic-function and/or may comprise an active-matrix liquid-crystal display or other flat panel display and/or an image sensor.
It is known to form semiconductor memories with non-volatile memory transistors, such as floating-gate transistors and dielectric-storage transistors. The memory state of a memory cell comprising a floating-gate transistor is determined by the charge state of a floating, additional gate electrode between the main gate and conduction channel of the transistor. The memory state of a memory cell comprising a dielectric-storage transistor is determined by the charge state at a storage site in the gate dielectric of the transistor. Normally the non-volatile memory transistor of a memory cell forms the memory storage element which is addressed by an individual selection transistor within that cell. Such a transistor arrangement for a memory cell is disclosed in, for example, FIGS. 7 and 13 to 16 of U.S. Pat. No. 4,586,065, the whole contents of which are hereby incorporated herein as reference material. In U.S. Pat. No. 4,586,065 the memory transistor is of the dielectric-storage type (for example the MNOS type having storage sites between layers of silicon nitride and of silicon oxide which form its gate dielectric) and has an advantageous specific geometry for its gate dielectric.
Japanese Patent Application Kokai JP-A-60-38799 discloses a less conventional arrangement of a non-volatile memory transistor in a memory cell. In this case, the memory cell includes a load driven by the non-volatile memory transistor. The whole contents of JP-A-60-38799 are hereby incorporated herein as reference material. The memory transistor has a conduction channel which is conductive in a first memory state of the memory transistor and which is less conductive in a second memory state of the memory transistor so as to provide a difference in signal at a node between the memory transistor and the load. The signal at this node is the output signal of this known memory cell. The memory transistor is of the floating-gate type. As illustrated in FIG. 4 of JP-A-60-38799, the transistor characteristics of the floating-gate memory transistor are not good enough to provide an adequate difference in the signal at the node between the memory transistor and the load, in the first and second memory states of the cell. Both a non-symmetric gate geometry and a particular circuit connection are adopted for this memory transistor of JP-A-60-38799, in order to obtain a sufficiently large difference in signal at the node between the memory transistor and the load, in the first and second memory state of the cell. Thus, the floating gate is localized so as to control the conduction channel adjacent the drain end of the transistor, but not adjacent to its source end. The drain is set to ground potential. The load is driven with the source of the memory transistor. Such a floating-gate memory transistor having this asymmetric gate geometry is not ideal for forming a low cost memory.
The memories disclosed in U.S. Pat. No. 4,586,065 and JP-A-60-38799 are of the monolithic semiconductor type which are usually formed in monocrystalline silicon. There is currently much interest in developing much larger area electronic devices using thin-film circuitry with, for example, amorphous or polycrystalline semiconductor films, on glass and on other inexpensive insulating substrates. U.S. Pat. No. 5,272,370 discloses one example of a thin-film memory device. The whole contents of U.S. Pat. No. 5,272,370 are hereby incorporated herein as reference material. In this case, the memory device is of the ROM type (read only memory), comprising thin-film diodes as the memory elements. There is a need for thin-film read-write memory devices comprising non-volatile memory transistors. Floating-gate and dielectric-storage memory transistors can be formed as thin-film devices, but their transistor characteristics are much worse than those for similar transistors formed in monocrystalline silicon. In particular, thin-film memory transistors have higher off-state leakage currents and poorer (i.e leakier) sub-threshold characteristics, both of which render more difficult the assembly of large numbers of such memory cells in a memory array.